This invention relates to a data transfer circuit, more particularly to a data transfer circuit performing electronic data transfer which is applicable to a microcomputer system and a microprocessor system including a central processing unit (CPU), peripheral I/O functions, memories for storing data, etc.
The microcomputer includes various peripheral I/O functions as interfaces for connecting peripheral devices for use in input-output of electronic data, and operates to transfer various electronic data among CPU, peripheral I/O functions, and memories through the data transfer circuit.
The JP/A/3-211687 discloses such a conventional data transfer circuit of this kind as shown in FIG. 5 attached hereto. In this figure, a data transfer circuit 100 is arranged including a CPU 101, an interrupt control portion 102, a program memory 103, a data memory 105 including a stack area 104, peripheral parts 106, a data bus 107, etc.
In this arrangement, when a certain processing is finished in the peripheral parts 106, this parts 106 outputs an interrupt signal to the interrupt control portion 102. At this time, if there is a state permitting the interrupt, the interrupt control portion 102 outputs an interrupt request signal to the CPU 101. When the CPU 101 receives this interrupt request signal, it interrupts execution of the current program, and has the current program address and various registers such as an arithmetic register, a control register, and a state register saved in the stack area 104. Then, the interrupt processing program is executed.
However, in case of transferring the operation result accomplished by the peripheral parts 106 with the interrupt processing by using the prior art data transfer circuit 100 like the above, it is inevitably required to save the program address indicating the execution state of the current main program and various registers before executing the interrupt processing program, and also to return all the above saved to their original state after terminating the interrupt processing program. furthermore, as a matter of course, the main program can not help suspending execution thereof during the interrupt processing, so that if the number of peripheral parts is increased and it is frequently requested to transfer the operation results accomplished by the peripheral parts, the operational efficiency of the CPU is naturally decreased. Especially, in case the peripheral parts have to continuously deal with a large amount of data, in order to storing the preprocessed results, it is required to execute the interrupt processing program so many times as well as to additionally provide a plurality of saving registers, thus the burden of the software and the hardware being increased. This is the problem to be improved or obviated.